idwt97_datapath.v

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

//`timescale 1ns/10ps
module IDWT97_DataPath(
	Clk,
	Reset,
	Sel,
	indata,
	
	
	outdata
	);

parameter Data_Width = 20;

input Clk;
input Reset;
input [4:0] Sel;

input [Data_Width-1:0] indata;

output [Data_Width-1:0] outdata;

wire [Data_Width-1:0] D1out;
wire [Data_Width-1:0] D2out;
wire [Data_Width-1:0] D3out;
wire [Data_Width-1:0] D4out;
wire [Data_Width-1:0] D5out;
wire [Data_Width-1:0] D6out;
wire [Data_Width-1:0] D7out;
wire [Data_Width-1:0] D8out;
wire [Data_Width-1:0] D9out;
wire [Data_Width-1:0] D10out;

wire [Data_Width-1:0] P1out;
wire [Data_Width-1:0] P2out;
wire [Data_Width-1:0] P3out;
wire [Data_Width-1:0] P4out;
wire [Data_Width-1:0] P5out;
wire [Data_Width-1:0] P6out;

wire [Data_Width-1:0] add_a1_out;
wire [Data_Width-1:0] add_a2_out;

wire [Data_Width-1:0] add_b1_out;
wire [Data_Width-1:0] add_b2_out;

wire [Data_Width-1:0] add_r1_out;
wire [Data_Width-1:0] add_r2_out;

wire [Data_Width-1:0] add_l1_out;
wire [Data_Width-1:0] add_l2_out;

wire [Data_Width-1:0] coff_a_out;
wire [Data_Width-1:0] coff_b_out;
wire [Data_Width-1:0] coff_r_out;
wire [Data_Width-1:0] coff_l_out;

wire sel_F;
wire sel_I;
assign sel_F = 1'b1;
assign sel_I = 1'b0;

Register_F D1(.Clk(Clk), .Clr(Reset), .Wen(Sel[3]), .Data_In(indata), .Out_Data(D1out));
Register_F D2(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(D1out), .Out_Data(D2out));
Register_F D3(.Clk(Clk), .Clr(Reset), .Wen(!Sel[3]), .Data_In(indata), .Out_Data(D3out));

//parameter l
Add add_a1(.InData_1(indata), .InData_2(D2out), .OutData(add_a1_out));
coff_l coff_l(.indata(add_a1_out), .sel(sel_I), .outdata(coff_a_out));
Add add_a2(.InData_1(coff_a_out), .InData_2(D3out), .OutData(add_a2_out));

Register_F P1(.Clk(Clk), .Clr(Reset), .Wen(Sel[3]), .Data_In(add_a2_out), .Out_Data(P1out));	//!Sel[3]
Register_F P2(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(D2out), .Out_Data(P2out));
Register_F D4(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(P1out), .Out_Data(D4out));

//parameter r
Add add_b1(.InData_1(P1out), .InData_2(D4out), .OutData(add_b1_out));
coff_r coff_r(.indata(add_b1_out), .sel(sel_I), .outdata(coff_b_out));
Add add_b2(.InData_1(coff_b_out), .InData_2(P2out), .OutData(add_b2_out));

Register_F P3(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(D4out), .Out_Data(P3out));
Register_F P4(.Clk(Clk), .Clr(Reset), .Wen(!Sel[3]), .Data_In(add_b2_out), .Out_Data(P4out));	//Sel[3]

//wire	[Data_Width-1:0]	temp1 = Sel[2] ? P3out : P4out;
//Register_F D5(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(temp1), .Out_Data(D5out));
Register_F D6(.Clk(Clk), .Clr(Reset), .Wen(Sel[3]), .Data_In(P4out), .Out_Data(D6out));
Register_F D7(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(P3out), .Out_Data(D7out));

//parameter b
Add add_r1(.InData_1(P4out), .InData_2(D6out), .OutData(add_r1_out));
coff_b coff_b(.indata(add_r1_out), .sel(sel_I), .outdata(coff_r_out));
Add add_r2(.InData_1(coff_r_out), .InData_2(D7out), .OutData(add_r2_out));	//D7out

Register_F P5(.Clk(Clk), .Clr(Reset), .Wen(Sel[3]), .Data_In(add_r2_out), .Out_Data(P5out));	//!Sel[3]
Register_F P6(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(D6out), .Out_Data(P6out));
Register_F D8(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(P5out), .Out_Data(D8out));

//parameter a
Add add_l1(.InData_1(P5out), .InData_2(D8out), .OutData(add_l1_out));
coff_a coff_a(.indata(add_l1_out), .sel(sel_I), .outdata(coff_l_out));
Add add_l2(.InData_1(coff_l_out), .InData_2(P6out), .OutData(add_l2_out));

//wire [Data_Width-1:0] temp2 = Sel[2] ? D8out : add_l2_out;

Register_F D9(.Clk(Clk), .Clr(Reset), .Wen(!Sel[3]), .Data_In(add_l2_out), .Out_Data(D9out));	//Sel[3]
Register_F D10(.Clk(Clk), .Clr(Reset), .Wen(sel_F), .Data_In(D8out), .Out_Data(D10out));
assign outdata = Sel[3] ? D9out : D10out;

endmodule