datapath_test.vhd

来自「for FPGA IMPLEMENTATION,OUR DATAPATH CRE」· VHDL 代码 · 共 51 行

-- ============================================================
-- File Name: datapath_test.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY datapath_test IS 
END datapath_test;

ARCHITECTURE behavior OF datapath_test IS

COMPONENT datapath
	PORT
	(
		clk	: IN STD_LOGIC;
		rst	: IN STD_LOGIC
	);
END COMPONENT;

CONSTANT clk_cycle : TIME := 20 ns;

SIGNAL t_clk	: STD_LOGIC;	
SIGNAL t_rst	: STD_LOGIC;
BEGIN
	
	U0 : datapath PORT MAP(clk => t_clk, rst => t_rst);
	
	PROCESS
	BEGIN
		t_clk <= '1';
		WAIT FOR clk_cycle/2;
		t_clk <= '0';
		WAIT FOR clk_cycle/2;
	END PROCESS;
	
	PROCESS
	BEGIN
		t_rst <= '1';
		WAIT FOR clk_cycle * 2;
		t_rst <= '0';
		WAIT;
	END PROCESS;

END behavior;