datapath.vhd

来自「for FPGA IMPLEMENTATION,OUR DATAPATH CRE」· VHDL 代码 · 共 92 行

-- ============================================================
-- File Name: datapath.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY datapath IS 
	PORT
	(
		clk			: IN STD_LOGIC;
		rst			: IN STD_LOGIC
		
--		memdr		: OUT STD_LOGIC;
--		wr 			: OUT STD_LOGIC;
--		ld_x		: OUT STD_LOGIC;
--		ld_y 		: OUT STD_LOGIC;
--		aludr		: OUT STD_LOGIC;
--		addr 		: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--		din_mem 	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--		dout_mem 	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--		funct		: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END datapath;

ARCHITECTURE structure OF datapath IS

COMPONENT memory
	PORT 
	(
		clk		: IN STD_LOGIC;
		wr		: IN STD_LOGIC;
		memdr	: IN STD_LOGIC;
		addr	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		din		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)		
	);
END COMPONENT;

COMPONENT control 
	PORT
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		din		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		ld_x	: OUT STD_LOGIC;
		ld_y	: OUT STD_LOGIC;
		aludr	: OUT STD_LOGIC;
		funct	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
		memdr	: OUT STD_LOGIC;
		wr		: OUT STD_LOGIC;
		addr	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT alu
	PORT
	(
		clk		: IN STD_LOGIC;
		ld_x	: IN STD_LOGIC;
		ld_y	: IN STD_LOGIC;
		aludr	: IN STD_LOGIC;
		funct	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		din		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

SIGNAL r_memdr, r_wr, r_ld_x, r_ld_y, r_aludr	: STD_LOGIC;
SIGNAL r_addr, r_din_mem, r_dout_mem			: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL r_funct	: STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGIN

--	memdr <= r_memdr;
--	wr <= r_wr;
--	ld_x <= r_ld_x;
--	ld_y <= r_ld_y;
--	aludr <= r_aludr;
--	addr <= r_addr;
--	din_mem <= r_din_mem;
--	dout_mem <= r_dout_mem;
--	funct <= r_funct;

	U0 : memory PORT MAP(clk, r_wr, r_memdr, r_addr, r_din_mem, r_dout_mem);
	U1 : control PORT MAP(clk, rst, r_dout_mem, r_ld_x, r_ld_y, r_aludr, r_funct, r_memdr, r_wr, r_addr);
	U2 : alu PORT MAP(clk, r_ld_x, r_ld_y, r_aludr, r_funct, r_dout_mem, r_din_mem);

END structure;