math_logic.vhd

来自「for FPGA IMPLEMENTATION,OUR DATAPATH CRE」· VHDL 代码 · 共 63 行

-- ============================================================
-- File Name: math_logic.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY math_logic IS 
	PORT
	(
		aludr	: IN STD_LOGIC;
		funct	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		xdin	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		ydin	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END math_logic;

ARCHITECTURE behavior OF math_logic IS

	SIGNAL xdin_int, ydin_int, dout_int	: INTEGER;
	
BEGIN

	PROCESS (aludr, funct, xdin, ydin)
	BEGIN
		IF (aludr = '0') THEN
				dout <= "ZZZZZZZZ";
		ELSE
			CASE funct IS
				WHEN "000" =>	xdin_int <= CONV_INTEGER(xdin);
								ydin_int <= CONV_INTEGER(ydin);
								dout_int <= xdin_int + ydin_int;
								dout <= CONV_STD_LOGIC_VECTOR(dout_int, 8);
					
				WHEN "001" => 	xdin_int <= CONV_INTEGER(xdin);
								ydin_int <= CONV_INTEGER(ydin);
								dout_int <= xdin_int - ydin_int;
								dout <= CONV_STD_LOGIC_VECTOR(dout_int, 8);
					
				WHEN "010" => 	xdin_int <= CONV_INTEGER(xdin);
								ydin_int <= CONV_INTEGER(ydin);
								dout_int <= xdin_int * ydin_int;
								dout <= CONV_STD_LOGIC_VECTOR(dout_int, 8);
					
				WHEN "011" => 	xdin_int <= CONV_INTEGER(xdin);
								ydin_int <= CONV_INTEGER(ydin);
								dout_int <= xdin_int / ydin_int;
								dout <= CONV_STD_LOGIC_VECTOR(dout_int, 8);
					
				WHEN "100" => 	dout <= xdin AND ydin;
				WHEN "101" => 	dout <= xdin OR ydin;
				WHEN "110" => 	dout <= xdin XOR ydin;
				WHEN "111" => 	dout <= xdin XNOR ydin;
					
				WHEN OTHERS =>	dout <= "XXXXXXXX";
			END CASE;
		END IF;	
	END PROCESS;

END behavior;