📄 datapath_struct.vhd
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-- -----------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the Aladdin Free Public License. --
-- Contact HT-Lab for commercial applications and/or support contracts. --
-- --
-- Full details of the license can be found in the file "cpu86_license.txt" --
-- which is included in the distribution zip file. --
-- -----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY datapath IS
PORT(
clk : IN std_logic;
clrop : IN std_logic;
instr : IN instruction_type;
iomem : IN std_logic;
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
path : IN path_in_type;
reset : IN std_logic;
wrpath : IN write_in_type;
abusdp_out : OUT std_logic_vector (19 DOWNTO 0);
dbusdp_out : OUT std_logic_vector (15 DOWNTO 0);
status : OUT status_out_type
);
END datapath ;
ARCHITECTURE struct OF datapath IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL alu_inbusa : std_logic_vector(15 DOWNTO 0);
SIGNAL alu_inbusb : std_logic_vector(15 DOWNTO 0);
SIGNAL alubus : std_logic_vector(15 DOWNTO 0);
SIGNAL aluopr : std_logic_vector(6 DOWNTO 0);
SIGNAL ax_s : std_logic_vector(15 DOWNTO 0);
SIGNAL bp_s : std_logic_vector(15 DOWNTO 0);
SIGNAL bx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ccbus : std_logic_vector(15 DOWNTO 0);
SIGNAL cs_s : std_logic_vector(15 DOWNTO 0);
SIGNAL cx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL data_in : std_logic_vector(15 DOWNTO 0);
SIGNAL di_s : std_logic_vector(15 DOWNTO 0);
SIGNAL dibus : std_logic_vector(15 DOWNTO 0);
SIGNAL dimux : std_logic_vector(2 DOWNTO 0);
SIGNAL disp : std_logic_vector(15 DOWNTO 0);
SIGNAL dispmux : std_logic_vector(2 DOWNTO 0);
SIGNAL div_err : std_logic;
SIGNAL domux : std_logic_vector(1 DOWNTO 0);
SIGNAL ds_s : std_logic_vector(15 DOWNTO 0);
SIGNAL dx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ea : std_logic_vector(15 DOWNTO 0);
SIGNAL eabus : std_logic_vector(15 DOWNTO 0);
SIGNAL eamux : std_logic_vector(3 DOWNTO 0);
SIGNAL es_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbus : std_logic_vector(15 DOWNTO 0);
SIGNAL ipreg : std_logic_vector(15 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL opmux : std_logic_vector(1 DOWNTO 0);
SIGNAL rm : std_logic_vector(2 DOWNTO 0);
SIGNAL sdbus : std_logic_vector(15 DOWNTO 0);
SIGNAL segbus : std_logic_vector(15 DOWNTO 0);
SIGNAL segop : std_logic_vector(2 DOWNTO 0);
SIGNAL selalua : std_logic_vector(3 DOWNTO 0);
SIGNAL selalub : std_logic_vector(3 DOWNTO 0);
SIGNAL seldreg : std_logic_vector(2 DOWNTO 0);
SIGNAL selds : std_logic;
SIGNAL selsreg : std_logic_vector(1 DOWNTO 0);
SIGNAL si_s : std_logic_vector(15 DOWNTO 0);
SIGNAL sibus : std_logic_vector(15 DOWNTO 0);
SIGNAL simux : std_logic_vector(1 DOWNTO 0);
SIGNAL sp_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ss_s : std_logic_vector(15 DOWNTO 0);
SIGNAL w : std_logic;
SIGNAL wralu : std_logic;
SIGNAL wrcc : std_logic;
SIGNAL wrd : std_logic;
SIGNAL wrip : std_logic;
SIGNAL wrop : std_logic;
SIGNAL wrs : std_logic;
SIGNAL wrtemp : std_logic;
SIGNAL xmod : std_logic_vector(1 DOWNTO 0);
signal domux_s : std_logic_vector(2 downto 0);
signal opreg_s : std_logic_vector(1 downto 0); -- Override Segment Register
signal opflag_s : std_logic; -- set if segment override in progress
signal eam_s : std_logic_vector(15 downto 0);
signal segsel_s : std_logic_vector(5 downto 0); -- segbus select
signal int0cs_s : std_logic;
-- Component Declarations
COMPONENT ALU
PORT (
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic ;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
w : IN std_logic ;
wralu : IN std_logic ;
wrcc : IN std_logic ;
wrtemp : IN std_logic ;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END COMPONENT;
COMPONENT dataregfile
PORT (
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic ;
wrd : IN std_logic ;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
clk : IN std_logic ;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT ipregister
PORT (
clk : IN std_logic ;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
wrip : IN std_logic ;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT segregfile
PORT (
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic ;
reset : IN std_logic ;
clk : IN std_logic ;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 Change N-Bit vector into individual signals/vectors
dimux <= path.datareg_input(6 downto 4); -- Data Register Input Path
w <= path.datareg_input(3);
seldreg <= path.datareg_input(2 downto 0);
-- selalua(4) & selalub(4) & aluopr(7)
selalua <= path.alu_operation(14 downto 11); -- ALU Path
selalub <= path.alu_operation(10 downto 7);
aluopr <= path.alu_operation(6 downto 0);
domux <= path.dbus_output; -- Data Output Path
simux <= path.segreg_input(3 downto 2); -- Segment Register Input Path
selsreg <= path.segreg_input(1 downto 0);
dispmux <= path.ea_output(9 downto 7); -- select ipreg addition
eamux <= path.ea_output(6 downto 3); -- 4 bits
segop <= path.ea_output(2 downto 0); -- segop(2)=override flag
-- HDL Embedded Text Block 2 eb2
-- eb2 Write Strobes
wrd <= wrpath.wrd;
wralu <= wrpath.wralu;
wrcc <= wrpath.wrcc;
wrs <= wrpath.wrs;
wrip <= wrpath.wrip;
wrop <= wrpath.wrop;
wrtemp<= wrpath.wrtemp;
-- HDL Embedded Text Block 3 eb3
-- eb3 3 Data Path Status
status.ax <= ax_s;
status.cx_one <= '1' when (cx_s=X"0001") else '0';
status.cx_zero <= '1' when (cx_s=X"0000") else '0';
status.cl5 <= cx_s(4 downto 0); -- 5 bits used for shift/rotate
status.flag <= ccbus;
status.div_err <= div_err; -- Divider overflow
-- HDL Embedded Text Block 4 eb4
-- eb4 4
disp <= instr.disp;
data_in <= instr.data;
nbreq <= instr.nb;
rm <= instr.rm;
xmod <= instr.xmod;
-- HDL Embedded Text Block 5 calcea
----------------------------------------------------------------------------
-- Determine effective address (eb5 5)
-- rm action
-- 000 ea = BX + SI + disp
-- 001 ea = BX + DI + disp
-- 010 ea = BP + SI + disp
-- 011 ea = BP + DI + disp
-- 100 ea = SI + disp
-- 101 ea = DI + disp
-- 110 ea = BP + disp (except when mod=00 then ea=disphigh,displow)
-- 111 ea = BX + disp
--
-- selds='1' when BP is NOT referenced (use DS in this case, else use SS)
-- xmod=mod
----------------------------------------------------------------------------
process (rm, ax_s,bx_s,cx_s,dx_s,bp_s,sp_s,si_s,di_s,disp,xmod)
begin
case rm is
when "000" => if xmod="11" then eam_s <= ax_s;
else eam_s <= bx_s + si_s + disp;
end if;
selds<='1';
when "001" => if xmod="11" then eam_s <= cx_s;
else eam_s <= bx_s + di_s + disp;
end if;
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