代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
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v com2s_16.v

`timescale 1ns/1ns module COM2S_16(datain, com2sout); //input signal input [15:0] datain; //output signal output [15:0] com2sout; wire [15:0] com2sout; assign com2sout = ~datain + 1'b1;
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v ham_code_16tt.v

`timescale 1ns/1ns module Ham_Code_16TT(); //input sig
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c constellation.c

/*****************************************************************************/ /* FIle Name : constellation.c */ /* Description : WiMax OFDM Subcarrier
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vhd mixofcarry.vhd

----//// Simulation is right; ---- Data: 2004,8,8; ---- MixOfCarry; ---- DataIn AmpOfCarry DataOut ---- +- 1; +- 1; +- 1; +- 2; ---- +- 3; +- 2; +- 3; +- 6; library IEE
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m psequence.m

function dataouts=Pseqence() datamids=0; dataouts=[]; dataout2=[]; S=[ones(1,7)]; for j=1:127 %length(datain) %if datain(j)==datamid % dataout1(j)=0; %else dataout1(j)=1;
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srr ddr_sdram.srr

$ Start of Compile #Fri Jun 30 17:00:38 2000 Synplicity VHDL Compiler, version 6.0.0, built May 19 2000 Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved VHDL syntax check successf
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htm ascii.htm

cpldfit: version H.42 Xilinx Inc. Fitter Report Design Name: dial1 Date: 2-21-2
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rpt dial1.rpt

cpldfit: version H.42 Xilinx Inc. Fitter Report Design Name: dial1 Date: 2-21-2006, 11:33AM Device
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v map_lpm_ram.v

module map_lpm_ram(dataout,datain,addr,we,inclk,outclk); input[15:0] datain; input[7:0] addr; input we,inclk,outclk; output[15:0] dataout; lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
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hier_info reg4.hier_info

|REG4 LOAD => DOUT[2]~reg0.CLK LOAD => DOUT[1]~reg0.CLK LOAD => DOUT[0]~reg0.CLK LOAD => DOUT[3]~reg0.CLK DIN[0] => DOUT[0]~reg0.DATAIN DIN[1] => DOUT[1]~reg0.DATAIN DIN[2] => DOUT[2]~reg0.DATA