mixofcarry.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

----//// Simulation is right;

----  Data: 2004,8,8;
     
----  MixOfCarry;

----  DataIn  AmpOfCarry  DataOut
----  +- 1;	+- 1;	 +- 1; +- 2;
----	 +- 3;	+- 2;	 +- 3; +- 6;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity MixOfCarry is
    Port ( SampleClk : in std_logic;
           DataIn : in std_logic_vector(1 downto 0);
           AmpOfCarry : in std_logic_vector(1 downto 0);
           DataOut : out std_logic_vector(2 downto 0));
end MixOfCarry;

architecture rtl of MixOfCarry is

    signal DataOfTemp : std_logic_vector(2 downto 0);

begin


    DataOfTemp(2) <= not ( DataIn(1) xor AmpOfCarry(1) );
    DataOfTemp(1) <= DataIn(0);
    DataOfTemp(0) <= AmpOfCarry(0);
    
    process(SampleClk)
    begin
       if SampleClk'event and SampleClk='1' then 
	      DataOut <= DataOfTemp;
	  end if;
    end process;     


end rtl;