com2s_16.v

来自「HAMMING CODE在偵錯及更正的原理實現」· Verilog 代码 · 共 14 行

`timescale 1ns/1ns

module COM2S_16(datain, com2sout);
//input signal
input	[15:0]	datain;
//output signal
output	[15:0]	com2sout;

wire	[15:0]	com2sout;

assign com2sout = ~datain + 1'b1;

endmodule