ddr_sdram.srr

DDR sdram 包含的完整的源码,仿真的相关文件

$ Start of Compile
#Fri Jun 30 17:00:38 2000

Synplicity VHDL Compiler, version 6.0.0, built May 19 2000
Copyright (C) 1994-2000, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

Synthesizing work.ddr_sdram.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_sdram.vhd":131:14:131:16|Port direction mismatch between component and entity
Synthesizing work.pll1.syn_black_box
Post processing for work.pll1.syn_black_box
Synthesizing work.ddr_data_path.rtl
Post processing for work.ddr_data_path.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal din2a[31:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal dq2[15:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal dmin2a[3:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal dm1[1:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":173:9:173:10|Feedback mux created for signal d2_oe. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":100:8:100:9|Feedback mux created for signal dataout[31:0]. Did you forget the set/reset assignment for this signal?
Synthesizing work.ddr_command.rtl
Post processing for work.ddr_command.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(7) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":271:9:271:10|Optimizing register bit rw_shift(3) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":271:9:271:10|Optimizing register bit rw_shift(2) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(6) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(5) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(4) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":52:2:52:4|Input nop is unused
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":58:2:58:6|Input sc_cl is unused
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":60:2:60:7|Input sc_rrd is unused
Synthesizing work.ddr_control_interface.rtl
Post processing for work.ddr_control_interface.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":93:9:93:10|Feedback mux created for signal load_reg1. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":93:9:93:10|Feedback mux created for signal load_reg2. Did you forget the set/reset assignment for this signal?
Post processing for work.ddr_sdram.rtl
@END
Process took 0.14 seconds realtime, 0.14 seconds cputime
Synplicity Altera Technology Mapper, version 6.0.0, built May 19 2000
Copyright (C) 1994-2000, Synplicity Inc.  All Rights Reserved
@N:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_sdram.vhd":361:4:361:6|Found black box instance work.ddr_sdram(rtl)-pll of view:work.pll1(syn_black_box) without an altera_area attribute. Reports will not include any lcells for this instance 
@N:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":222:9:222:10|Found counter in view:work.ddr_control_interface(rtl) inst timer[15:0]
Automatic dissolve during optimization of view:work.ddr_sdram(rtl) of control1(ddr_control_interface)
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":164:9:164:10|Removing sequential instance control1.SC_CL[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":164:9:164:10|Removing sequential instance control1.SC_RRD[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":164:9:164:10|Removing sequential instance control1.SC_RRD[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":164:9:164:10|Removing sequential instance control1.SC_RRD[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":164:9:164:10|Removing sequential instance control1.SC_RRD[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":93:9:93:10|Removing sequential instance control1.NOP of view:PrimLib.dffr(prim) because there are no references to its outputs 
Created 128 cliques with a total of 256 instances along critical paths
Created 0 cliques with a total of 0 instances along critical paths
Found clock clk100_inferred_clock with period 5ns
Found clock clk200_inferred_clock with period 5ns

		 ##### START TIMING REPORT #####

		 Performance Summary 
		*********************

                          Requested     Estimated     Requested     Estimated          
Clock                     Frequency     Frequency     Period        Period        Slack
---------------------------------------------------------------------------------------
clk100_inferred_clock     200.0 MHz     78.9 MHz      5.0           12.7          -7.7 
clk200_inferred_clock     200.0 MHz     122.7 MHz     5.0           8.2           -3.2 
=======================================================================================

		 Interface Information 
		***********************

Input Ports: 

Port            Reference                           User           Arrival     Required            
Name            Clock                               Constraint     Time        Time         Slack  
---------------------------------------------------------------------------------------------------
ADDR[0]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[1]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[2]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[3]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[4]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[5]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[6]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[7]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[8]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[9]         clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[10]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[11]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[12]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[13]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[14]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[15]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[16]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[17]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[18]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[19]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[20]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
ADDR[21]        clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
CLK             System                              0.0            0.0         >2000.0      >2000.0
CMD[0]          clk100_inferred_clock [rising]      0.0            0.0         -0.1         -0.1   
CMD[1]          clk100_inferred_clock [rising]      0.0            0.0         -0.1         -0.1   
CMD[2]          clk100_inferred_clock [rising]      0.0            0.0         -0.1         -0.1   
DATAIN[0]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[1]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[2]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[3]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[4]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[5]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[6]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[7]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[8]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[9]       clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[10]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[11]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[12]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[13]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[14]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[15]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[16]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[17]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[18]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[19]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[20]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[21]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[22]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[23]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[24]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[25]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[26]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[27]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[28]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[29]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[30]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[31]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[32]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[33]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[34]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[35]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[36]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[37]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2    
DATAIN[38]      clk100_inferred_clock [rising]      0.0            0.0         0.2          0.2