代码搜索：async_fifo
找到约 10 项符合「async_fifo」的源代码
代码结果 10
www.eeworm.com/read/323403/13341193
list system_tb.list
../sim/system_tb.v
2 ../sim/unisims/DCM_SP.v
3 ../sim/unisims/BUFG.v
4 ../sim/unisims/FDDRRSE.v
5 ../sim/ddr/ddr.v
6 ../rtl/async_fifo.v
7 ../rtl/ddr_clkgen.v
8 ../rtl/ddr_pulse78.v
9 ../rtl/d
www.eeworm.com/read/323403/13341129
prj system.prj
1 verilog work ../rtl/ddr_clkgen.v
2 verilog work ../rtl/ddr_pulse78.v
3 verilog work ../rtl/ddr_ctrl.v
4 verilog work ../rtl/ddr_init.v
5 verilog work ../rtl/ddr_rpath.v
6 verilog work ../rtl/dd
www.eeworm.com/read/213706/15127535
xco my_async_fifo.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = T:\xprojects\coregen_examples\async_fifo\verilog\61i_async_fifo_v5_1_ver_ise
SET
www.eeworm.com/read/306506/13743056
v async_fifo.v
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 4;
output [DATA_WIDTH-1:0] rdata;
output
www.eeworm.com/read/457110/7334119
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output
www.eeworm.com/read/404203/11490439
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output
www.eeworm.com/read/339746/12206636
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output
www.eeworm.com/read/395931/8145673
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output
www.eeworm.com/read/395559/8168216
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output
www.eeworm.com/read/369664/9637393
v async_fifo.v
// FIFO顶层模块
module async_fifo (rdata, wfull, rempty, wdata,
wreq, wclk, wrst_n, rreq, rclk, rrst_n);
parameter DATA_WIDTH = 8; // FIFO数据位宽
parameter ADDR_WIDTH = 4; // FIFO地址位宽
output