system.prj

ddr ram controller vhdl code

1 verilog work ../rtl/ddr_clkgen.v 
2 verilog work ../rtl/ddr_pulse78.v 
3 verilog work ../rtl/ddr_ctrl.v 
4 verilog work ../rtl/ddr_init.v 
5 verilog work ../rtl/ddr_rpath.v 
6 verilog work ../rtl/ddr_wpath.v 
7 verilog work ../rtl/async_fifo.v 
8 verilog work ../rtl/gray_counter.v 
9 verilog work ../rtl/rotary.v 
10 verilog work ../bench/fml_memtest.v 
11 verilog work ../bench/system.v 
12 verilog work ../bench/lac/lac.v 
13 verilog work ../bench/lac/dp_ram.v 
14 verilog work ../bench/lac/uart.v