system_tb.list

ddr ram controller vhdl code

../sim/system_tb.v 
2 ../sim/unisims/DCM_SP.v 
3 ../sim/unisims/BUFG.v 
4 ../sim/unisims/FDDRRSE.v 
5 ../sim/ddr/ddr.v 
6 ../rtl/async_fifo.v 
7 ../rtl/ddr_clkgen.v 
8 ../rtl/ddr_pulse78.v 
9 ../rtl/ddr_init.v 
10 ../rtl/gray_counter.v 
11 ../rtl/rotary.v 
12 ../rtl/ddr_rpath.v 
13 ../rtl/ddr_wpath.v 
14 ../rtl/ddr_ctrl.v 
15 ../bench/fml_memtest.v 
16 ../bench/system.v 
17 ../bench/lac/lac.v 
18 ../bench/lac/dp_ram.v 
19 ../bench/lac/uart.v