my_async_fifo.xco

XILINX的FPGA实现的双口ram源码

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = T:\xprojects\coregen_examples\async_fifo\verilog\61i_async_fifo_v5_1_ver_ise
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = T:\xprojects\coregen_examples\async_fifo\verilog\61i_async_fifo_v5_1_ver_ise
SET device = xc2v40
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = cs144
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1
# END Select
# BEGIN Parameters
CSET create_rpm=false
CSET read_acknowledge=true
CSET almost_empty_flag=true
CSET write_acknowledge=true
CSET memory_type=block
CSET read_acknowledge_sense=active_high
CSET read_count_width=2
CSET fifo_depth=15
CSET component_name=my_async_fifo
CSET write_count_width=2
CSET write_count=true
CSET read_count=true
CSET write_error=true
CSET read_error=true
CSET read_error_sense=active_high
CSET almost_full_flag=true
CSET write_acknowledge_sense=active_high
CSET write_error_sense=active_high
CSET input_data_width=16
# END Parameters
GENERATE