design_top.v

来自「XILINX的FPGA实现的双口ram源码」· Verilog 代码 · 共 56 行

module design_top (
	din,
	wr_en,
	wr_clk,
	rd_en,
	rd_clk,
	ainit,
	dout,
	full,
	empty,
	almost_full,
	almost_empty,
	wr_count,
	rd_count,
	rd_ack,
	rd_err,
	wr_ack,
	wr_err);

input [15 : 0] din;
input wr_en;
input wr_clk;
input rd_en;
input rd_clk;
input ainit;
output [15 : 0] dout;
output full;
output empty;
output almost_full;
output almost_empty;
output [1 : 0] wr_count;
output [1 : 0] rd_count;
output rd_ack;
output rd_err;
output wr_ack;
output wr_err;

	my_async_fifo u0(
		.din(din),
		.wr_en(wr_en),
		.wr_clk(wr_clk),
		.rd_en(rd_en),
		.rd_clk(rd_clk),
		.ainit(ainit),
		.dout(dout),
		.full(full),
		.empty(empty),
		.almost_full(almost_full),
		.almost_empty(almost_empty),
		.wr_count(wr_count),
		.rd_count(rd_count),
		.rd_ack(rd_ack),
		.rd_err(rd_err),
		.wr_ack(wr_ack),
		.wr_err(wr_err));
endmodule