async_fifo.v

verilog

module async_fifo (rdata, wfull, rempty, wdata,
					wreq, wclk, wrst_n, rreq, rclk, rrst_n);
	parameter DATA_WIDTH = 8;			
	parameter ADDR_WIDTH = 4;			
	output [DATA_WIDTH-1:0] rdata;
	output wfull;
	output rempty;
	input [DATA_WIDTH-1:0] wdata;
	input wreq, wclk, wrst_n;
	input rreq, rclk, rrst_n;

	wire [ADDR_WIDTH-1:0] wptr, rptr;
	wire [ADDR_WIDTH-1:0] waddr, raddr;
	wire aempty_n, afull_n;
	dp_ram  dp_ram(.rdata(rdata), 		
				   .wdata(wdata),
				   .waddr(wptr), 
				   .raddr(rptr),
				   .wclken(wreq), 
				   .wclk(wclk));
		defparam dp_ram.DATA_WIDTH = DATA_WIDTH,
				 dp_ram.ADDR_WIDTH = ADDR_WIDTH;

	async_cmp async_cmp(.aempty_n(aempty_n), 
						.afull_n(afull_n),
						.wptr(wptr), 
						.rptr(rptr), 
						.wrst_n(wrst_n));
		defparam async_cmp.ADDR_WIDTH = ADDR_WIDTH;
				
	rptr_empty rptr_empty(.rempty(rempty), 	
						  .rptr(rptr),
						  .aempty_n(aempty_n), 
						  .rreq(rreq),
						  .rclk(rclk), 
						  .rrst_n(rrst_n));
		defparam rptr_empty.ADDR_WIDTH = ADDR_WIDTH;
								
	wptr_full wptr_full(.wfull(wfull), 	
						.wptr(wptr),
						.afull_n(afull_n), 
						.wreq(wreq),
						.wclk(wclk), 
						.wrst_n(wrst_n));
		defparam wptr_full.ADDR_WIDTH = ADDR_WIDTH;
endmodule