代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/415944/11047011
vhd adder.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity adder is
Port( x,y: in std_logic_vector(15 downto 0);
cin : in std_logic;
sum : out st
www.eeworm.com/read/415793/11053669
vhd adder.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY adder IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Cout
www.eeworm.com/read/415793/11053673
vhd adder.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGI
www.eeworm.com/read/415793/11053683
vhd adder.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD
www.eeworm.com/read/415793/11053726
vhd adder.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
ENTITY adder IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGI
www.eeworm.com/read/415793/11053824
vhd adder.vhd
---------- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: Adde
www.eeworm.com/read/413144/11165287
vhd adder.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:10:40 11/03/2008
-- Design Name:
-- Module Name: adder - Be
www.eeworm.com/read/411380/11247788
vhd adder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder is
Port (reset1:in std_logic;
clina1:in std_logic_vector(3 do
www.eeworm.com/read/335286/12541188
v adder.v
module adder(cout,sum,a,b,cin);
parameter size=16;
output cout;
output[size-1:0] sum;
input cin;
input[size-1:0] a,b;
assign {cout,sum}=a+b+cin;
endmodule
www.eeworm.com/read/147268/12570700
vhd adder.vhd
ENTITY adder IS
PORT
(
clk :IN BIT;
SET1:IN BIT;
SET2:IN BIT;
SECH:OUT BIT_VECTOR(3 DOWNTO 0);
SECL:OUT INTEGER RANGE 0 TO 16;
MINH:OUT BIT_VECTOR(3 DOWNTO 0);
MINL:OUT BIT_VE