adder.vhd

来自「用VHDL编写的数字时钟,可变宽度脉冲产生器」· VHDL 代码 · 共 30 行

ENTITY adder IS
PORT 
( 
  clk :IN BIT;
  SET1:IN BIT;
  SET2:IN BIT;
  SECH:OUT BIT_VECTOR(3 DOWNTO 0);
  SECL:OUT INTEGER RANGE 0 TO 16;
  MINH:OUT BIT_VECTOR(3 DOWNTO 0);
  MINL:OUT BIT_VECTOR(3 DOWNTO 0);
  HOUH:OUT BIT_VECTOR(3 DOWNTO 0);
  HOUL:OUT BIT_VECTOR(3 DOWNTO 0)
);
END adder;
ARCHITECTURE a OF adder IS
BEGIN
	PROCESS (clk)
		VARIABLE	cnt		: INTEGER RANGE 0 TO 16;	
		BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF SET1 = '0' AND SET2='0' THEN
			cnt := cnt + 1;
			END IF;
		END IF;

		SECL<=cnt;
	END PROCESS;

END a;