adder.vhd

来自「采用VHDL语言设计了一个打铃系统。该系统已经调试」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder is
    Port (reset1:in std_logic;
	       clina1:in std_logic_vector(3 downto 0);
			 clinb1:in std_logic_vector(3 downto 0);
	       mina1:in std_logic_vector(3 downto 0);
			 minb1:in std_logic_vector(3 downto 0);
			 sina1:in std_logic_vector(3 downto 0);
			 sinb1:in std_logic_vector(3 downto 0);
			 zout1:out integer
			 );
end adder;

architecture Behavioral of adder is

begin

process(reset1,clina1,clinb1,mina1,minb1,sina1,sinb1)
variable bzout,bzout1,bzout2:integer;
    begin
	 if reset1='0' then
	     bzout1:=conv_integer(clina1)*3600+conv_integer(mina1)*60+conv_integer(sina1);
		   bzout2:=conv_integer(clinb1)*36000+conv_integer(minb1)*600+conv_integer(sinb1)*10;
			bzout:=bzout1+bzout2;
		  else
		    bzout:=0;
     end if;
	        zout1<=bzout;
end process;

end Behavioral;