adder.vhd

an implementation of fft 1024 with cos and sin generated by matlab.

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:10:40 11/03/2008 
-- Design Name: 
-- Module Name:    adder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity adder is 
      generic ( 
               inst_width : INTEGER := 32);            
     port (  
           inst_A : in std_logic_vector(inst_width-1 downto 0);   
           inst_B : in std_logic_vector(inst_width-1 downto 0);     
            SUM : out std_logic_vector(inst_width downto 0) ); 
    end adder;

architecture oper of adder is 
signal a_signed, b_signed, sum_signed: SIGNED(inst_width downto 0); 
begin 
   a_signed <= SIGNED(inst_A(inst_width-1) & inst_A); 
    b_signed <= SIGNED(inst_B(inst_width-1) & inst_B);
        sum_signed <= a_signed + b_signed; 
  SUM <= std_logic_vector(sum_signed); 
end oper;