multiplier.vhd

来自「an implementation of fft 1024 with cos a」· VHDL 代码 · 共 48 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:02:29 11/03/2008 
-- Design Name: 
-- Module Name:    multiplier - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier is 
      generic ( 
inst_width1 : INTEGER := 16;             
inst_width2 : INTEGER := 16);   
    port (   
     inst_A : in std_logic_vector(inst_width1-1 downto 0);        
     inst_B : in std_logic_vector(inst_width2-1 downto 0);        
     PRODUCT_inst : out std_logic_vector(inst_width1 +  inst_width2 - 1 downto 0)); 
	  end multiplier; 
 
architecture oper of multiplier is 
  signal mult_sig : SIGNED(inst_width1+inst_width2-1 downto 0) ;  
 
begin 
  mult_sig <= SIGNED(inst_A) * SIGNED(inst_B);  
PRODUCT_inst <= std_logic_vector(mult_sig);         
end oper;