adder.vhd

来自「2008年北京市大学生电子设计竞赛程序源代码[测频率」· VHDL 代码 · 共 33 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;

Entity   adder is  
Port(   x,y: in  std_logic_vector(15 downto 0);
        cin : in std_logic;
        sum : out std_logic_vector(15 downto 0);
        cout: out std_logic );
End adder;

Architecture a of adder is
Signal c: std_logic_vector(0 to 4);

Component bcdadder
Port(  a,b : in  std_logic_vector(3 downto 0);
        ci : in std_logic;
    result : out std_logic_vector(3 downto 0);
        co : out std_logic );
end component;

Begin
c(0)<=cin;
U1: bcdadder Port map(x(3 downto 0),y(3 downto 0),c(0),sum(3 downto 0),c(1));
U2: bcdadder Port map(x(7 downto 4),y(7 downto 4),c(1),sum(7 downto 4),c(2));
U3: bcdadder Port map(x(11 downto 8),y(11 downto 8),c(2),sum(11 downto 8),c(3));
U4: bcdadder Port map(x(15 downto 12),y(15 downto 12),c(3),sum(15 downto 12),c(4));
cout<=c(4);
End a;