代码搜索结果

library verilog; use verilog.vl_types.all; entity crc_send is generic( WIDTH : integer := 1; AMOUNT : integer := 8 ); port( data_send : out

library verilog; use verilog.vl_types.all; entity max is port( max_num : out vl_logic_vector(3 downto 0); clk : in vl_logic; rst : in

library verilog; use verilog.vl_types.all; entity lev is port( level : out vl_logic_vector(3 downto 0); lev_ena : in vl_logic; clk : in

本书简要介绍了<mark>Verilog</mark>硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是<mark>Verilog</mark> HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。 ...

version 3 D:/Homework/ISE8.1 work/pa_ser/se_pa.v se_pa VERILOG VERILOG se_pa_tst.xwv Clocked - - 1000000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEGIN clk 100000000 100000000

library verilog; use verilog.vl_types.all; entity time_going is port( clk : in vl_logic_vector(0 downto 0); clr : in vl_logic_vector(0 downto 0);

library verilog; use verilog.vl_types.all; entity datact1 is port( data : out vl_logic_vector(7 downto 0); \in\ : in vl_logic_vector(7 downto 0);

library verilog; use verilog.vl_types.all; entity counter is port( pc_addr : out vl_logic_vector(12 downto 0); ir_addr : in vl_logic_vector(12 downto 0);

library verilog; use verilog.vl_types.all; entity ddr_command is port( clk : in vl_logic; reset_n : in vl_logic; saddr : in vl_log

library verilog; use verilog.vl_types.all; entity mt46v4m16 is generic( addr_bits : integer := 12; data_bits : integer := 16; col_bits : integer := 8;