_primary.vhd

用VHDL写的运动计时表程序

library verilog;
use verilog.vl_types.all;
entity time_going is
    port(
        clk             : in     vl_logic_vector(0 downto 0);
        clr             : in     vl_logic_vector(0 downto 0);
        load            : in     vl_logic_vector(0 downto 0);
        data_sec        : in     vl_logic_vector(7 downto 0);
        data_min        : in     vl_logic_vector(7 downto 0);
        data            : in     vl_logic_vector(7 downto 0);
        out_sec         : out    vl_logic_vector(7 downto 0);
        out_min         : out    vl_logic_vector(7 downto 0);
        \out\           : out    vl_logic_vector(7 downto 0)
    );
end time_going;