_primary.vhd

来自「在quaters下写的比较数的大小输出」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity max is
    port(
        max_num         : out    vl_logic_vector(3 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        max_ena         : in     vl_logic;
        out_max_en      : in     vl_logic;
        data_in         : in     vl_logic_vector(3 downto 0)
    );
end max;