_primary.vhd

来自「循环冗余校验」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity crc_send is
    generic(
        WIDTH           : integer := 1;
        AMOUNT          : integer := 8
    );
    port(
        data_send       : out    vl_logic_vector;
        data_in         : in     vl_logic_vector;
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        ready           : out    vl_logic
    );
end crc_send;