_primary.vhd

来自「精简CPU设计」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity datact1 is
    port(
        data            : out    vl_logic_vector(7 downto 0);
        \in\            : in     vl_logic_vector(7 downto 0);
        data_ena        : in     vl_logic
    );
end datact1;