_primary.vhd

来自「在quaters下写的比较数的大小输出」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity lev is
    port(
        level           : out    vl_logic_vector(3 downto 0);
        lev_ena         : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        max_number      : in     vl_logic_vector(3 downto 0)
    );
end lev;