代码搜索结果

m255 13 cModel Technology dE:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec T_opt V1?n;Q1Qb?XT9gl2iECM]G0 04 14 4 work test_match_rec

Synplicity Xilinx Technology Mapper, Version 8.8.0p, Build 069R, Built Apr 17 2007 19:41:05 Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved Product Version Version 8.8.0.4 Reading con

Selecting top level module match_rec @N: CG364 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":21:7:21:15|Synthesizing

#Build: Synplify Pro 8.8.0.4, Build 008R, Dec 7 2006 #install: D:\Program\FPGA_software\Synplicity\fpga_8804 #OS: Windows XP 5.1 #Hostname: USER-73B7470377 #Implementation: match_rec #Fri Ju

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

library verilog; use verilog.vl_types.all; entity parity is port( data_in : in vl_logic_vector(7 downto 0); ctrl_mode : in vl_logic; rst_l :

library verilog; use verilog.vl_types.all; entity hamdec is port( data_in : in vl_logic_vector(7 downto 0); ham_in : in vl_logic_vector(3 downto 0);

library verilog; use verilog.vl_types.all; entity control is port( clk1 : out vl_logic; cnt_for_mux : out vl_logic_vector(4 downto 0); cnt