sap.log

使用VERILOG实现QPSK信号的匹配滤波

Synplicity Xilinx Technology Mapper, Version 8.8.0p, Build 069R, Built Apr 17 2007 19:41:05
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8.0.4
Reading constraint file: E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.sdc
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
Reading Xilinx I/O pad type table from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/gttype.txt> 


@N: BN225 |Writing default property annotation file E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.sap.
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 06 16:59:59 2008

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