_primary.vhd

奇偶校验码的VERILOG源码

library verilog;
use verilog.vl_types.all;
entity parity is
    port(
        data_in         : in     vl_logic_vector(7 downto 0);
        ctrl_mode       : in     vl_logic;
        rst_l           : in     vl_logic;
        data_out        : out    vl_logic_vector(8 downto 0)
    );
end parity;