match_rec.tlg

使用VERILOG实现QPSK信号的匹配滤波

Selecting top level module match_rec
@N: CG364 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":21:7:21:15|Synthesizing module match_rec

@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":67:10:67:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":68:10:68:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":72:12:72:15|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":75:10:75:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":80:12:80:15|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":81:10:81:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":88:10:88:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":89:10:89:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":94:12:94:15|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":97:10:97:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":101:10:101:13|Removing redundant assignment
@N: CG179 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":102:10:102:13|Removing redundant assignment
@W: CL169 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":31:2:31:7|Pruning Register cnt4[2:0]