_info

使用VERILOG实现QPSK信号的匹配滤波

m255
13
cModel Technology
dE:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec
T_opt
V1?n;Q1Qb?XT9gl2iECM]G0
04 14 4 work test_match_rec fast 0
04 4 4 work glbl fast 0
o-quiet -auto_acc_if_foreign -work work -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip
tExplicit 1
OE;O;6.2b;35
vglbl
I@25W]P_?R2MF58_YTL5O=0
VnN]4Gon>inod6>M^M2[SV1
dE:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec
w1202685744
FD:/Program/FPGA_software/ISE10.1/ISE/verilog/src/glbl.v
L0 5
VnN]4Gon>inod6>M^M2[SV1
OE;L;6.2b;35
r1
31
o+acc
vmatch_rec
IT6GJY;MXa]<;EZN][nN0=1
VhJcK`Y1>1I;Ff6;6lSA8l1
dE:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec
w1212760382
Fmatch_rec.v
L0 21
VhJcK`Y1>1I;Ff6;6lSA8l1
OE;L;6.2b;35
r1
31
o+acc
vtest_match_rec
IBc1fk_h0ALgzfQkKGQi9?0
V65S`oQOUg><GK>RClRETC3
dE:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec
w1212827036
Ftest_match_rec.v
L0 25
V65S`oQOUg><GK>RClRETC3
OE;L;6.2b;35
r1
31
o+acc