_primary.vhd

来自「汉明码的编结码模块」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity hamdec is
    port(
        data_in         : in     vl_logic_vector(7 downto 0);
        ham_in          : in     vl_logic_vector(3 downto 0);
        data_out        : out    vl_logic_vector(7 downto 0);
        error           : out    vl_logic
    );
end hamdec;