代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dds is
port(
clk : in vl_logic;
reset : in vl_logic;
k : in vl_logic_vecto
file.f
./addr_fifo.v
./ddr2_sodimm.v
./ddr2.v
./dma_ddr2_if.v
./mem_interface_top_black_box.v
./mem_interface_top_ctrl_0.v
./mem_interface_top_ddr2_top_0.v
./mem_interface_top_idelay_ctrl.v
./mem_interface_t
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity alu is
generic(
ALUOP_ADD : integer := 0;
ALUOP_SUB : integer := 8;
ALUOP_AND : integer := 1;
AL
voptqq72vx
library verilog;
use verilog.vl_types.all;
entity registerfile is
port(
RF_Addr_A : in vl_logic_vector(3 downto 0);
RF_Addr_B : in vl_logic_vector(3 downto 0);
vopt56i9xh
library verilog;
use verilog.vl_types.all;
entity armdatapath is
port(
A_Addr_Sel : in vl_logic_vector(1 downto 0);
B_Addr_Sel : in vl_logic;
RF_Addr_Writ
vopt31e5ab
library verilog;
use verilog.vl_types.all;
entity ALU_ARM7 is
port(
Alu_A : in vl_logic_vector(31 downto 0);
Alu_B : in vl_logic_vector(31 downto 0);
voptj2wx6z
library verilog;
use verilog.vl_types.all;
entity registerfile is
port(
RF_Addr_A : in vl_logic_vector(3 downto 0);
RF_Addr_B : in vl_logic_vector(3 downto 0);
voptagcikr
library verilog;
use verilog.vl_types.all;
entity armdatapath is
port(
A_Addr_Sel : in vl_logic_vector(1 downto 0);
B_Addr_Sel : in vl_logic;
RF_Addr_Writ
vopttdwztr
library verilog;
use verilog.vl_types.all;
entity ALU_ARM7 is
port(
Alu_A : in vl_logic_vector(31 downto 0);
Alu_B : in vl_logic_vector(31 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity armdatapath is
port(
A_Addr_Sel : in vl_logic_vector(1 downto 0);
B_Addr_Sel : in vl_logic;
RF_Addr_Writ