vopt56i9xh

ARM10 INSTALALTION GUIDE

library verilog;
use verilog.vl_types.all;
entity armdatapath is
    port(
        A_Addr_Sel      : in     vl_logic_vector(1 downto 0);
        B_Addr_Sel      : in     vl_logic;
        RF_Addr_Write_Sel: in     vl_logic_vector(2 downto 0);
        RF_Bus_Write_Sel: in     vl_logic_vector(2 downto 0);
        RF_PC_Write_Sel : in     vl_logic_vector(3 downto 0);
        RF_Load_Write   : in     vl_logic;
        RF_Load_Flags   : in     vl_logic;
        RF_PSR_R_Sel    : in     vl_logic;
        RF_PSR_W_Sel    : in     vl_logic;
        RF_PSR_Read     : out    vl_logic_vector(31 downto 0);
        SC_Type         : in     vl_logic_vector(4 downto 0);
        SC_Source       : in     vl_logic_vector(3 downto 0);
        SZE_Sel         : in     vl_logic_vector(1 downto 0);
        SZE_Ctrl        : in     vl_logic;
        SAM_Ctrl        : in     vl_logic_vector(1 downto 0);
        BS_Input_Sel    : in     vl_logic;
        BS_Enable       : in     vl_logic;
        BS_Cin          : in     vl_logic;
        AR_Bus_ALU_Sel  : in     vl_logic_vector(1 downto 0);
        AR_Bus_Sel      : in     vl_logic_vector(1 downto 0);
        WD_DBE          : in     vl_logic;
        WD_Load         : in     vl_logic;
        nOPC            : out    vl_logic;
        nCPI            : out    vl_logic;
        CPA             : in     vl_logic;
        CPB             : in     vl_logic;
        ALU_A_Sel       : in     vl_logic_vector(1 downto 0);
        Alu_Cntrl       : in     vl_logic_vector(4 downto 0);
        Multiplier_Enable: in     vl_logic;
        Multiplier_Ready: out    vl_logic;
        ir2_bus         : out    vl_logic_vector(31 downto 0);
        ir2_mult_bus    : out    vl_logic_vector(31 downto 0);
        ir1_zero        : in     vl_logic;
        ir2_zero        : in     vl_logic;
        ld_ir2_mult     : in     vl_logic;
        nSTALL          : in     vl_logic;
        BBus_Src        : in     vl_logic;
        sysclk          : in     vl_logic;
        nRESET          : in     vl_logic;
        nFIQ            : in     vl_logic;
        nIRQ            : in     vl_logic;
        ALU_Hold_Enable : in     vl_logic;
        ALU_Hold_Sel    : in     vl_logic;
        Link_Sel        : in     vl_logic;
        A_MAR           : out    vl_logic_vector(31 downto 0);
        D               : inout  vl_logic_vector(31 downto 0)
    );
end armdatapath;