file.f

sata_device_model,对做硬盘控制器的朋友有帮助

./addr_fifo.v
./ddr2_sodimm.v
./ddr2.v
./dma_ddr2_if.v
./mem_interface_top_black_box.v
./mem_interface_top_ctrl_0.v
./mem_interface_top_ddr2_top_0.v
./mem_interface_top_idelay_ctrl.v
./mem_interface_top_infrastructure.v
./mem_interface_top_mem_if_top_0.v
./mem_interface_top_phy_calib_0.v
./mem_interface_top_phy_ctl_io_0.v
./mem_interface_top_phy_dm_iob.v
./mem_interface_top_phy_dq_iob.v
./mem_interface_top_phy_dqs_iob.v
./mem_interface_top_phy_init_0.v
./mem_interface_top_phy_io_0.v
./mem_interface_top_phy_top_0.v
./mem_interface_top_phy_write_0.v
./mem_interface_top_usr_addr_fifo_0.v
./mem_interface_top_usr_backend_fifo_0.v
./mem_interface_top_usr_ram_d_0.v
./mem_interface_top_usr_rd_0.v
./mem_interface_top_usr_rd_fifo_0.v
./mem_interface_top_usr_top_0.v
./mem_interface_top_usr_wr_fifo_0.v
./mem_interface_top.v
./mgt_usrclk_source.v
./rdfifo_128_32.v
./sata_gtp_tile.v
./sata_gtp.v
./sata_hdd_vcs.v
./shdd_model.v
./wrfifo_32_128.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/RAM16X1D.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/FIFO36.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/FIFO36_72.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/AFIFO36_INTERNAL.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/BUFIO.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/ODDR.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/FDP.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/IOBUFDS.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/IOBUF.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/FDPE.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/OBUF.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/OBUFDS.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/FDCPE.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/IBUFGDS_LVPECL_25.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/IDELAYCTRL.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/BUFG.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/IBUFDS.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/FD.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_4.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/DCM_BASE.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/DCM_ADV.v
/mnt/eda1/Xilinx10.1/ISE/smartmodel/lin/wrappers/vcsmxverilog/GTP_DUAL_FAST.v
/mnt/eda1/Xilinx10.1/ISE/verilog/src/unisims/GTP_DUAL.v