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来自「ARM10 INSTALALTION GUIDE」· 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity ALU_ARM7 is
    port(
        Alu_A           : in     vl_logic_vector(31 downto 0);
        Alu_B           : in     vl_logic_vector(31 downto 0);
        Alu_C           : in     vl_logic;
        Alu_Cntrl       : in     vl_logic_vector(4 downto 0);
        Alu_Signals     : out    vl_logic_vector(3 downto 0);
        Alu_Result      : out    vl_logic_vector(31 downto 0)
    );
end ALU_ARM7;