_primary.vhd

来自「用Verilog 编写的8位risc cpu」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity alu is
    generic(
        ALUOP_ADD       : integer := 0;
        ALUOP_SUB       : integer := 8;
        ALUOP_AND       : integer := 1;
        ALUOP_OR        : integer := 2;
        ALUOP_XOR       : integer := 3;
        ALUOP_COM       : integer := 4;
        ALUOP_ROR       : integer := 5;
        ALUOP_ROL       : integer := 6;
        ALUOP_SWAP      : integer := 7
    );
    port(
        op              : in     vl_logic_vector(3 downto 0);
        a               : in     vl_logic_vector(7 downto 0);
        b               : in     vl_logic_vector(7 downto 0);
        y               : out    vl_logic_vector(7 downto 0);
        cin             : in     vl_logic;
        cout            : out    vl_logic;
        zout            : out    vl_logic
    );
end alu;