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Verilog 的代码
pa_se.tap
n work pa_se verilog;
gi out[0];
ai .slack_logic 997.000 ;
gp Q[0];
ap .slack_logic 997.000 ;
gp D[0];
ap .slack_logic 997.000 ;
gp C;
ap .is_clock 1;
gi i[31:0];
ai .slack_logic 997.0
pa_se.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file pa_s
se_pa.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file se_p
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sub_cf is
port(
a : in vl_logic_vector(3 downto 0);
b : in vl_logic_vector(3 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity people4 is
port(
a : in vl_logic_vector(0 downto 0);
b : in vl_logic_vector(0 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sec60 is
port(
clk : in vl_logic;
clr : in vl_logic;
load : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity time60 is
port(
cin : out vl_logic;
cin_min : in vl_logic_vector(0 downto 0);
load :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity machine is
generic(
HLT : integer := 0;
SKZ : integer := 1;
ADD : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity \register\ is
port(
opc_iraddr : out vl_logic_vector(15 downto 0);
data : in vl_logic_vector(7 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity adr is
port(
addr : out vl_logic_vector(12 downto 0);
fetch : in vl_logic;
ir_addr : i