_primary.vhd

来自「这是我自己写的4人表决器源码」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity people4 is
    port(
        a               : in     vl_logic_vector(0 downto 0);
        b               : in     vl_logic_vector(0 downto 0);
        c               : in     vl_logic_vector(0 downto 0);
        d               : in     vl_logic_vector(0 downto 0);
        e               : out    vl_logic
    );
end people4;