_primary.vhd

来自「精简CPU设计」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity \register\ is
    port(
        opc_iraddr      : out    vl_logic_vector(15 downto 0);
        data            : in     vl_logic_vector(7 downto 0);
        ena             : in     vl_logic;
        clk1            : in     vl_logic;
        rst             : in     vl_logic
    );
end \register\;