_primary.vhd

精简CPU设计

library verilog;
use verilog.vl_types.all;
entity machine is
    generic(
        HLT             : integer := 0;
        SKZ             : integer := 1;
        ADD             : integer := 2;
        \AND\           : integer := 3;
        \XOR\           : integer := 4;
        LDA             : integer := 5;
        STO             : integer := 6;
        JMP             : integer := 7
    );
    port(
        inc_pc          : out    vl_logic;
        load_acc        : out    vl_logic;
        load_pc         : out    vl_logic;
        rd              : out    vl_logic;
        wr              : out    vl_logic;
        load_ir         : out    vl_logic;
        datact1_ena     : out    vl_logic;
        halt            : out    vl_logic;
        clk1            : in     vl_logic;
        zero            : in     vl_logic;
        ena             : in     vl_logic;
        opcode          : in     vl_logic_vector(2 downto 0)
    );
end machine;