_primary.vhd

来自「精简CPU设计」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity adr is
    port(
        addr            : out    vl_logic_vector(12 downto 0);
        fetch           : in     vl_logic;
        ir_addr         : in     vl_logic_vector(12 downto 0);
        pc_addr         : in     vl_logic_vector(12 downto 0)
    );
end adr;