_primary.vhd

来自「用VHDL写的运动计时表程序」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity sec60 is
    port(
        clk             : in     vl_logic;
        clr             : in     vl_logic;
        load            : in     vl_logic;
        data_sec        : in     vl_logic_vector(7 downto 0);
        out_sec         : out    vl_logic_vector(7 downto 0);
        cin_min         : out    vl_logic
    );
end sec60;