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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bus_operation_FPGAB is
generic(
A1 : integer := 15375;
A2 : integer := 197571;
A3 :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode_BPSK is
generic(
Uncode : integer := 0;
Code12 : integer := 1;
Code34 : integer := 2
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode12test is
port(
code_out12 : out vl_logic;
code_clk12 : out vl_logic;
add_cy_31_bit : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bit_stat is
port(
bit_clk : in vl_logic;
bit_data : in vl_logic_vector(2 downto 0);
reset
div3.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = E:\TL_verilog_final\TL_AUTO_SYN_BPSK_CY
SET speedgrade = -11
SET simulationfiles
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity transmitter is
generic(
IDLE : integer := 16;
STOP1 : integer := 10;
STOP2 : integer := 11;
image_ram_tb.v
//
// Verilog Module dwt_final_lib.image_ram_tb.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 10:26:53 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.
vopt6t8jzi
library verilog;
use verilog.vl_types.all;
entity k_counter is
port(
Kclock : in vl_logic;
reset : in vl_logic;
dnup : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity k_counter is
port(
Kclock : in vl_logic;
reset : in vl_logic;
dnup : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity DPLL is
port(
sys_clock : in vl_logic;
reset : in vl_logic;
enable : in vl_logic;