image_ram_tb.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.image_ram_tb.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 10:26:53 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module image_ram_tb;
  
   reg clk,reset;
   reg  [7:0] in;
   reg  [13:0] addr;
   reg r_w_en;
   wire [7:0] out;
   integer k,i;
        
   initial
   begin
     $readmemb("D:/image_input.txt",ram1.mem);
     k= $fopen("D:/image_output.txt");

     clk=1'b0;
     reset=1'b1;
     r_w_en=1'b1;
     addr=14'd0;
     #8 reset=1'b0;
     #5 reset=1'b1;
     #10000
     for(i=0;i<=8191;i=i+1)
      $fdisplayb(k,ram1.mem[i]);
    
     
     #1000 $finish;     
     
   end
   
   always
   #10 clk=!clk;
   
   always
   begin
   #20 addr=addr+14'd1; 
   //$fopen("D:/image_output.txt");
   //$writememh("D:/image_output.txt",ram1.mem); 
 end
   
  
  image_ram ram1(clk,reset,in,out,addr,r_w_en);


// ### Please start your Verilog code here ###
endmodule