_primary.vhd

来自「一个实现简单的数字锁相环Verilog代码」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity k_counter is
    port(
        Kclock          : in     vl_logic;
        reset           : in     vl_logic;
        dnup            : in     vl_logic;
        enable          : in     vl_logic;
        Kmode           : in     vl_logic_vector(2 downto 0);
        carry           : out    vl_logic;
        borrow          : out    vl_logic
    );
end k_counter;