div3.xco

采用匹配滤波

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = E:\TL_verilog_final\TL_AUTO_SYN_BPSK_CY
SET speedgrade = -11
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = E:\TL_verilog_final\TL_AUTO_SYN_BPSK_CY
SET device = xc4vlx60
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff668
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex4
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Pipelined_Divider family Xilinx,_Inc. 3.0
# END Select
# BEGIN Parameters
CSET signed_b=Unsigned
CSET has_aclr=false
CSET divclk_sel=1_Clock
CSET fractional_b=Integer
CSET divisor_width=3
CSET component_name=div3
CSET fractional_width=3
CSET dividend_width=31
CSET sync_enable=CE_Overrides_SCLR
CSET has_sclr=false
CSET has_ce=false
# END Parameters
GENERATE