_primary.vhd

一个实现简单的数字锁相环Verilog代码

library verilog;
use verilog.vl_types.all;
entity DPLL is
    port(
        sys_clock       : in     vl_logic;
        reset           : in     vl_logic;
        enable          : in     vl_logic;
        Fin             : in     vl_logic;
        Fout            : out    vl_logic;
        Kmode           : in     vl_logic_vector(2 downto 0)
    );
end DPLL;