_primary.vhd

采用匹配滤波

library verilog;
use verilog.vl_types.all;
entity bus_operation_FPGAB is
    generic(
        A1              : integer := 15375;
        A2              : integer := 197571;
        A3              : integer := 787200;
        A4              : integer := 983232;
        B               : integer := 1431655765;
        \null\          : integer := 0
    );
    port(
        CTRL_CLK        : in     vl_logic;
        clk10           : in     vl_logic;
        reset_in        : in     vl_logic;
        reset           : in     vl_logic;
        CTRL_BUS        : inout  vl_logic_vector(35 downto 0);
        RST_DAC         : out    vl_logic;
        DAC_SCLK        : out    vl_logic;
        DAC_SDENB       : out    vl_logic;
        DAC_SDIO        : inout  vl_logic;
        E_data          : out    vl_logic_vector(30 downto 0);
        F_data          : out    vl_logic_vector(25 downto 0);
        G_data          : out    vl_logic_vector(25 downto 0);
        E_code          : out    vl_logic_vector(30 downto 0);
        F_code          : out    vl_logic_vector(25 downto 0);
        G_code          : out    vl_logic_vector(25 downto 0);
        E_fs            : out    vl_logic_vector(30 downto 0);
        F_fs            : out    vl_logic_vector(25 downto 0);
        G_fs            : out    vl_logic_vector(25 downto 0);
        load            : out    vl_logic;
        add_cy_31_bit   : out    vl_logic_vector(30 downto 0);
        clk_numb        : out    vl_logic_vector(15 downto 0);
        biaoshi         : out    vl_logic_vector(1 downto 0);
        modulate        : out    vl_logic_vector(3 downto 0);
        reset_m         : out    vl_logic
    );
end bus_operation_FPGAB;